In flash memory devices, such as ones based on NROM (nitride read only memory) technology, a successful read operation should be performed with minimum latency (also known as random access). The read operation involves applying a voltage to the NROM cell gate so that enough read current is flowing in the cell. The cell gate voltage level may be larger then the available VCC supply. For example (although not necessarily), the read voltage level may be around 4 V, whereas the VCC supply may be about 2.7 V. Accordingly, a charge pump circuit is typically used to generate an internal high voltage level to generate the read voltage level.
Since the charge pump operation consumes a significant amount of power, it is undesirable or impossible to keep it running during stand-by mode. Instead, the read voltage is typically maintained and floated by means of a large capacitor in the internal power supply and the charge pump may be switched off. However, the charge on the capacitor tends to leak over time. In order to solve the leakage problem, the charge pump circuitry replenishes the large capacitor of the internal power supply at a pre-defined internal frequency.
One method used in the prior art to replenish the internal power supply is by generating a high-power pulse that activates the internal circuitry. The high-power pulse may be generated by means of an oscillator (e.g., a free running ring oscillator), timer or voltage sensing circuit, for example. As is known in the art, this may require a bias, either in the form of an electric current or voltage or both generated by an external circuit. However, it is problematic to control the frequency and duty cycle of the high-power pulse generation so that the internal power supply is replenished with minimum power dissipation during standby. The capacitor leakage, being the reason for the replenishment, tends to grow exponentially with temperature. This fact imposes greater challenges for solving the problems mentioned above.
Some applications require a variation of the replenishment period as a function of temperature and/or of power supply voltage (usually a shorter period for high temperature and for low voltage). This is commonly accomplished in the art by introducing a temperature and/or supply voltage coefficient to the generator bias, although other schemes are possible.
The replenish pulse forming circuit and some circuits that are fed by the replenish pulse signal are usually designed in such a way as to source a minimum amount of electric current from the power supply between replenish pulses (referred to as the time when the pulse is de-asserted). Maintaining low electric current may extend battery operation life in portable applications, and may reduce heat energy dissipation, thereby extending the operating life and reliability of the system.
FIG. 1 shows a typical block diagram for the prior art implementation described above.
A current bias source 1 generates a DC current 2. The current source 1 generates the current as a function of a power supply voltage 3 and IC (integrated circuit) temperature 4. The bias current from current source 1 drives a ring oscillator 5.
Ring oscillator 5 may comprise three NMOS (n-channel metal oxide semiconductor) transistors 14, 15 and 16, whose gates are all connected to one another. The sources of the NMOS transistors 14, 15 and 16 may be grounded. The drains of the NMOS transistors 14, 15 and 16 are connected as inputs to inverters 17, 18 and 19, respectively (any odd number of inverter may be used). The inverters are connected in series with capacitors 20, 21 and 22, respectively connected to the inverter outputs. The output of inverter 19 is input to inverter 17. The gate of NMOS transistor 14 may be connected to the gate of another NMOS transistor 12. The drain of the NMOS transistor 12 may be connected to its gate, and its source may be grounded.
NMOS transistors 12, 14, 15 and 16 form a current mirror. In a current mirror one transistor is “diode connected”, which in the case of MOS transistors means the gate terminal is connected to the drain terminal (as in NMOS transistor 12) and one or more other transistors (NMOS transistors 14, 15 and 16) are connected with their gate terminals to the first transistor's gate while all source terminals are also connected together to the same voltage (such as ground in this example). In this manner, a gate-source voltage is generated between the connected gate terminals and the connected source terminals, and a secondary current is generated in the drain terminals of each of the NMOS transistors 14, 15 and 16.
The output pulse period of ring oscillator 5 shortens in response to a rise in bias current. The oscillator output period is multiplied using a frequency divider 6 and fed to a pulse generator 7, which drives circuitry such as the internal power supply 8, and charges a supply capacitor 10. All of the components 1–8 may be fed DC current from an external power source 9.
However, the bias generating circuit used to generate the high-power pulse must generally remain in operation continuously in order to guarantee generation of succeeding trigger signals that trigger the pulses. The bias circuit typically consumes most of the total supply current at the time when the pulse is de-asserted.